Today's advanced silicon technology allows for very low on-resistance power MOSFETs, enabling the use of small chips operating at very high power densities. In many cases, package resistance can be equal to the Silicon resistance—this is a very uneconomical use of the device Silicon. There is constant thrust to lower cost by decreasing package resistance. Due to the higher power densities, there is a need to have packages with lower thermal resistance. Package parasitic inductance can contribute to a majority of the power dissipated in the MOSFET in high frequency switching applications as in switch-mode power supplies. This problem becomes more severe as lower device resistances and improved technology allow for higher operating currents for the same package size.
With reference to FIG. 1, a top view of a conventional semiconductor package 1 having a leadframe 8 and die 10 molded in a plastic body 16 is illustrated. In this exemplary prior art embodiment, the die 10 embodies a MOSFET device and the leadframe 8 includes a source terminal 11, a gate terminal 12 and a drain terminal 13. Source terminal 11 of the leadframe 8 includes a plurality of separate source leadframe fingers or leads 11b external to the plastic body 16 and a plurality of separate internal source bonding areas 11a where the bond wires 14 are bonded. The drain terminal 13 includes a plurality of separate drain leadframe fingers or leads 13b which are connected to the leadframe pad 13a. The gate terminal 12 includes an external gate lead 12b connected to an internal gate bonding area 12a, the bonding area 12a is connected to a gate pad 17 via wire 15.
FIG. 2 illustrates a top view of another conventional semiconductor package 19. In this embodiment, in lieu of a plurality of separate source bonding area 11a as shown in FIG. 1, the source bonding area 21a of the source terminal 21 is joined to form a single source bonding area 21a for bonding wires 24 to die 20. As with the embodiment of FIG. 1, the separate source leadframe fingers or leads 21b and the separate leadframe drain fingers or leads 23b of drain 23 are separate narrow metal strips that radiate externally from the plastic body 26 and are adapted to be inserted into the same receptacle location on a PC board as the device embodied in FIG. 1.
Similar to the embodiment of FIG. 1, the leadframe pad 23a has die 20 disposed thereon and provides a generally narrow border frame around the perimeter of die 20. Moreover, the bonding area 22a of gate 22 is coupled via wire 25 to gate pad 27 formed at the nearest corner. In the prior art embodiments, the source and gate bonding areas 11a, 21a and 12a, 22a share the same left side of the die 10, 20. Likewise, the source leads 21b and the gate lead 22b radiate from the same left side.
Referring now a FIG. 3, a top view of a conventional dual-die semiconductor package 29 is shown. The dual-die semiconductor package 29 having a plastic body 36 that includes a first die 30 disposed over a first leadframe pad 33a and a second die 40 disposed over a second leadframe pad 43a. The first source terminal 31 includes at least one source leadframe lead 31b and a source bonding area 31a distributed along the left side of the first die 30. The source bonding area 31a is interconnected to the first die 30 via bond wires 34. The first gate terminal 32 has a gate bonding area 32a that shares the left side of the first die 30 and a gate leadframe lead 32b. The gate bonding area 32a is connected to the gate pad via bond wire 35. The first drain terminal 33 includes a plurality of separate drain leadframe leads 33b that are coupled to the first leadframe pad 33a. 
Similar to the first die 30, the second source terminal 41 includes at least one source leadframe lead 41b and a source bonding area 41a distributed along the left side of the second die 40. The source bonding area 41a is coupled to die 40 via bond wires 44. The second gate terminal 42 has a gate bonding area 42a that shares the left side of the second die 40 and a gate leadframe lead 42b. Bond wire 45 is used for interconnection. The second drain terminal 43 includes a plurality of separate drain leadframe leads 43b that are coupled to the second leadframe pad 43a. 
As explained before there is a need to reduce package electric resistance, inductance and enhance power dissipation for a metal-oxide semiconductor (MOSFET) device that is able to carry high electric current loading with a new leadframe and package design.
We have determined that by utilizing some of the real estate in the package's plastic body, by decreasing the size of the die and the leadframe pad, to increase the bonding area in order to increase the interconnections between the source terminal and the die, the electric resistance and inductance of the package can be reduced. The reduction in resistance comes from having more wires in parallel, while the improvement inductance comes from not only having more wires in parallel, but from spreading them further part, thereby reducing the mutual coupling inductance between wires.
Furthermore, increasing the surface area of the external source and drain leads, exposed to air, reduces external terminal resistance and allows heat to be dissipated quicker.
As will be seen more fully below, the present invention is substantially different in structure, methodology and approach from that of prior IC packages and leadframe designs.